An ultra-low power bus
Publications related to MBus
We have two refereed conference publications and two journal articles on MBus. The Top Picks article provides a slightly less technical overview of MBus, covering the design motivations and key architectural tenets for an interconnect for microscale systems. The ISCA ’15 publication takes a holisitic view of the ultra-low power and micro-scale system design space, identifies the architectural constraints, and walks through the design choices and methodology of MBus. The CICC ’14 publication introduces the novel circuit designs that enable MBus, and the JSTS ’16 article expands these arguments and adds details from implemented systems.
MBus: A system integration bus for the modular microscale computing class
IEEE Micro Top Picks '16
MBus is a new interchip interconnect made of two “shoot-through” rings that resolves fundamental size and power issues that prevent the design of composable microscale systems. MBus introduces power-oblivious communication, which guarantees message reception regardless of the recipient's power state. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts.
MBus: A Fully Synthesizable Low-power Portable Interconnect Bus for Millimeter-scale Sensor Systems
Journal of Semiconductor Technology and Science, Vol.16, No.6
This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180nm process. The entiresystem consumes 8nW in standby mode, and the bus achieves 17.5pJ/bit/chip.
MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems
ISCA '15
As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized—yet reusable—components with an interconnect that permits tiny, ultra-low power systems. In contrast to today’s interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead.
We present MBus, a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two “shoot-through” rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power-management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts.
To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus’s feature set.
MBus: A 17.5 pJ/bit/chip Portable Interconnect Bus for Millimeter-Scale Sensor Systems with 8 nW Standby Power
CICC '14
We propose an ultra-low power interconnect bus for millimeter-scale wireless sensor nodes. Using only 4 IO pads, the bus minimizes the required chip real estate, enabling ultra-small form factors in modular sensor node designs. Low power is achieved using a “clockless” design of member nodes while aggressive power gating allows an ultra-low power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with PMUs that have a special low power standby mode. The MBus is fully synthesizable and uses robust timing. Implemented in a 3 module system in 180 nm technology, Mbus achieves 8nW of standby power and 17.5 pJ/bit/chip.